The present invention relates to an evaluation device for evaluating electric characteristics of a connection portion made of a contact, a via or the like in a semiconductor device formed on a wafer.
Contacts and vias which are used in a semiconductor device and are for bringing a substrate surface into electrical conduction in the vertical direction to a substrate surface are one of important components. Thus, characteristics of contacts and vias are one of important evaluation items not only in developing a semiconductor process but also in fabricating a semiconductor device in mass production. Note that, in general, means for electrically connecting an active layer (doped layer) and an interconnect located over the active layer is called “contact” and means for electrically connecting a lower layer interconnect and an upper layer thereon interconnect is called “via”.
There are two items which should be evaluated in terms of evaluation of a contact and a via. A first item is whether or not a resistance value of a contact or a via as an initial characteristic is increased, compared to a design value. A second item is reliability. For example, whether or not a resistance value of a contact or a via is increased, compared to an initial value, after a stress (temperature or current) accelerated test is performed should be evaluated.
Hereinafter, a known evaluation device for evaluating a semiconductor device will be described with reference to the accompanied drawings (see e.g., Japanese Patent Publication No. 2630219)